This application claims priority to Korean Patent Application No. 2004-72472, filed on Sep. 10, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly, to generation of test mode signals for testing a memory device with minimized wiring.
2. Description of the Related Art
Recently, test circuits are included in a memory device to detect defects within the memory devices early so that such defects may be corrected. However, the addition of test circuits to a memory device increases the size of the memory device. The test circuits also require an increase in the number of internal signal buses, thereby further increasing the size of the memory device.
When the memory device is put into a test mode by the test circuits, the memory device stops normal operations and performs a testing operation. As the operating speed of a memory device increases, signal margin is reduced with a conventional method of setting the memory device in the test mode. In addition, the memory device may not be able to enter the test mode when operating at high speed.
FIG. 1 shows a block diagram of a conventional test mode signal generating circuit in a memory device. Referring to FIG. 1, the conventional test mode signal generating circuit includes an address decoding circuit 13 to generate test mode signals. When a command signal indicates via a command pin 11 that the memory device is to operate in a test mode, the address decoding circuit 13 generates a plurality of test mode signals 14 (TMRS1, TMRS2, . . . , and TMRSj) based on address information input via address pins 12 (Addr0, Addr1, . . . , and Addri). Each of the generated test mode signals 14 are transmitted to a respective one of test circuits 15 (CKT1, CKT2, . . . , and CKTj). The test circuits 15 perform testing in the memory device using the test mode signals 14.
FIG. 2 shows a block diagram of another conventional test mode signal generating circuit in a memory device. The test mode signal generating circuit of FIG. 2 includes a stage decoding circuit 26 in addition to the elements included in FIG. 1. To generate more test mode signals in FIG. 2 than in FIG. 1, the stage decoding circuit 26 in FIG. 2 generates signal type information indicating the types of test mode signals to be generated based on address information input via address pins 22 (Addr0, Addr1, . . . , and Addri). An address decoding circuit 23 generates the test mode signals 24 (TMRS1, TMRS2, . . . , and TMRSk) in response to the signal type information received from the stage decoding circuit 26 and the address information from the address pins 22.
Both of the test mode signal generating circuits of FIGS. 1 and 2 require address decoding circuits to generate the test mode signals. In other words, test commands are decoded differently according to input addresses, and test mode signals corresponding to the respective addresses are generated.
The test mode signal generating circuits of FIGS. 1 and 2 require bus lines to transmit the generated test mode signals to corresponding test circuits 15 or 25. Since an address decoding method is used, the number of test mode signals is determined by the number of addresses. The test mode signal generating circuit of FIG. 2 is different from the test mode signal generating circuit of FIG. 1 in that the former can generate a large number of test mode signals regardless of the number of addresses.
However, they are the same in that both require bus lines to transmit the generated test mode signals. Since the conventional test mode signal generating circuits of FIGS. 1 and 2 require numbers of bus lines equal to the numbers of generated test mode signals, the size of a memory device including one of the test mode signal generating circuits increases accordingly.
Further, the test mode signal generating circuits of FIGS. 1 and 2 require a process of latching an address decoded signal using a normal clock signal of the memory device. In that case, a sufficient margin between the address decoded signal and the normal clock signal is required. However, when the memory device operates at high speed, the margin between the address decoded signal and the normal clock signal is reduced. In particular, in the case of a high speed memory device, such as those recently developed, it is not easy to determine whether a test mode signal is set properly with respect to the high speed clock signal of the memory device.